I refused to connect my TV to the internet and use a Vero V for all of my watching needs. The Vero V is absolutely worse than most other experiences, but I'm happy.
I'd say that Ukraine were very prepared for the invasion, though? They managed to survive for the first 2 weeks, leading to a long-term war. The Donbas war had already been going on for 8 years, and I don't think Ukrainians were under some illusion that those weren't Russians.
It's quite unfortunate that traced references has to be wrapped in Gc<>, as this means that your types are bound to a GC allocator (right? Maybe I'm wrong!). It also means that trying out a GC is a pain, as you're stuck first doing the rewrite of your types. The necessity of Trace is another burden, but probably an unavoidable one.
In this example, you wrap Gc types in Option, I think that having the Gc type be nullable instead would be an interesting experiment. Having to introduce a lot of places that branch both puts more into the instruction cache, and adds more places that the branch predictor has to track. Besides, you can always add in missing checks if you know that you have a sparse subgraph somewhere. Total potential micro optimization, but it's a bit of fun :-).
I also like how this shows how freelists are a smidge less efficient in safe Rust, as compared to unsafe Rust. In this solution, we have to encode the tag for the discriminated union, this is unnecessary! The unoccupied slots forms its own separate list, and so you know that you will always have unoccupied slots as long as you trace along that path. I assume that that will add up to the maximum alignment of bytes, as arrays need to be well-aligned? So, probably 8 extra bytes per element (you're storing stuff that probably references other stuff).
I think it should be possible to get rid of the Option tag without introducing any unsafe code by changing index in Gc from u32 to std::num::NonZero<u32>.
So, I get that we charge the capacitor up, and that it leaks so we must recharge it periodically. I don't get two things:
1. How is the value read? Is it reading the leak?
2. How is recharging done? I guess the leak itself (assuming my guess in 1. holds) could provide charge for some logic that checks "if has charge then recharge else nop".
I still don't really get transistors :P, but this was cool.
You measure the charge (if it is there) before it is completely gone (if it were ever there). Capacitors always leak, these capacitors leak fast.
Measuring the charge also removes some of the charge -- fast, compared to the leak spead.
DRAM chips have a circuit that writes the value back -- charges the capacitor up if there's supposed to be a charge, drains it if there's not supposed to be a charge.
Refreshes and normal reads are the same, except that normal reads sends the value(s) to the output pin(s) on the chip.
He has "only" shown the basic grid of capacitors and transistors. The chip he shown has no circuit to measure charges or to write them back afterwards. This makes it easier to test the basic grip and the basic capcacitors.
Pretty sure the proper read out and write back circuit comes in the next video.
A transistor effectively is an AND gate. If there is a charge on both the source and the gate, then charge can move to drain. So if you charge up the capacitor and you connect it to the source of another transistor then you can check whether it is still charged by putting a charge to the gate and see if there is charge on the drain.
And you are right, that charge on the drain can then be used both to drive some logic and to activate the recharging of the capacitor that was just discharged.
By the way I am being handwavy about "charge" moving about, if you really want to learn the electronics it is more correct to call it a voltage relative to some ground that the charge always moves towards.
It turns out they intentionally drain a bit of the storage capacitor, and amplify that weak signal. Some of that amplified charge is then fed back to storage.
In the "real" DRAM chip, there is a large array of very tiny capacitors, with the switches which allow to connect one row of the array at a time to the readout column wires.
The capacitance of the wires themselves is typically an order of magnitude greater than that of the storage capacitors. So when the memory is read, the wires are first precharged to some standard voltage. Then the desired row of storage capacitors is connected to the wires, and the charges from the storage capacitors spread onto the wires, changing their voltages very slightly. These voltage deviations from the standard value are amplified by the "sense amplifiers". The amplifiers are sort of like flip-flops. Once they start in a state which "tilts" slightly to "zero" or slightly to "one", they go all the way to the full magnitude zeros and ones. This not only amplifies the signal, but also automatically brings the voltages on the wires and the still connected to them capacitors to the full magnitude, thus "refreshing" the data. The row is disconnected, and the next read cycle can start for some other row.
In the video, an array of 4x5 capacitors and the associated with them switches was fabricated. The capacitors in the video are several hundred times larger (12400 fF) than typical capacitors in a 64 Kbit DRAM (about 50 fF). I assume this is done so that in the later episodes the author could implement the readout electronics outside of the chip.
- any two conductive plates close together with an insulator between make a capacitor (1)
- when a capacitor is charged, the energy goes into the electric FIELD
- that's the FIELD of the field effect transistor
- if the field is strong enough, that causes conduction between source and drain (along the "channel")
- the insulator is nanometers thick, so current leaks across it; at that scale, you can detect individual electrons quantum teleporting straight through it.
(1) technically like gravity there is a capacitance between any two objects in the universe, but it's only significant when you have relatively wide and close conductors
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